Diode array and process for making same



May 7, 1968 c. J. CARTER ETAL 3,

DIODE ARRAY AND PROCESS FOR MAKING SAME 2 Sheets-Sheet 1 Original FiledSept. 29, 1961 wk w J 6 m C Richard F. Stewart fimflwmgm ATTORNEYS (3.J. CARTER YEITAL DIODE ARRAY AND PROCESS FOR MAKING SAME Original FiledSept. 29, 1961 May 7, 1968 2 Sheets-Sheet 2 INVENTOR6' Clarence J'arfier,

Rickard E'Stewarf A'ITORNEYS United States Patent 3,382,115 DIODE ARRAYAND PROCESS FOR MAKING SAME Clarence J. Carter, Rolling Hills Estate,and Richard F.

Stewart, Los Angeles, Calif., assignors to Texas InstrumentsIncorporated, Dallas, Tex., a corporation of Delaware Continuation ofapplication Ser. No. 141,854, Sept. 29, 1961. This application June 30,1965, Ser. No. 468,276 7 Claims. (Cl. 148-187) This is a continuationapplication of our copending application, Ser. No. 141,854, filed Sept.29, 1961, now abandoned.

This invention relates to a process of making a diode array on thesurface of a slab or wafer of semiconductor material and to the productresulting from this process.

In the field of radar telescopy there is need for an array of a largenumber of diodes spaced very close together. Such an array of diodeswould be useful to detect microwave energy focused by the lens system ofa radar telescope. To carry out this detection with individual existingdiodes assembled together into an array would be impractical because ofthe large number of diodes needed. On the order of one-half milliondiodes are required in the array. Also the physical size of such diodeswould make the resolution obtained by an assembled array very poor. Inview of the foregoing and other difficulties, it has not been possibleto date to devise a diode array that is satisfactory for radar telescopywork.

This invention, however, provides a way to overcome the difficult andtedious problems that have plagued those laboring in this field, andprovides a successful diode array. This is essentially accomplished byutilizing an integral diode array, sensitive to microwave energy, thatis formed on the surface of a slab or wafer of silicon. The wafer ofsilicon is characterized with a high resistivity to prevent microwavelosses and to prevent the diodes themselves from being shorted out.Whereas the use of high purity silicon is suggested for this purpose,such silicon is hard to get and expensive, especially in the amountcontemplated. To overcome this problem, a material that has an energylevel that lies deep in the forbidden energy band is diffused as animpurity material into the silicon. The addition of this material drivesthe silicon to a very high resistivity and in this way a lower puritysilicon can be used as a raw material and the desired high resistivitycan still be obtained. The preferred material for this purpose is gold.Iron or copper could also be used, but they do not work as well as gold.The diodes are formed on the silicon in unique ways as will become moreapparent from the detailed description appearing hereinafter.

It is, accordingly, an object of the present invention to provide anovel diode array that is especially adapted for radar telescopy.

It is a further object of the invention to provide a unique method forproducing a diode array for radar telescopy whereby an extraordinarynumber of diodes can be arranged compactly on a surface to obtain goodresolution of impinging signals on the diode array.

It is still another object of the invention to provide a diode arraythan can be readily manufactured economically and efficiently.

Further objects andadvantages of the invention will become readilyapparent from the following detailed description of a preferredembodiment of the invention and when taken in conjunction with thefollowing drawings wherein:

FIGURE 1 shows a silicon wafer as it appears during processing;

FIGURE 2 is a view in section taken along line 2--2 of FIGURE 1;

FIGURE 3 is a view in section taken along line 3-3 of FIGURE 2; and

FIGURE 4 shows the finished product.

According to the invention, the diode array is formed on a silicon waferor slab which may by way of example be about one inch square and 0.050inch thick. In accordance with the principles of this invention, thesilicon must possess a high resistivity as in use of the finished diodearray. The energy (microwave type) will pass through the wafer beforestriking the PN junction areas formed in one face of the wafer. In thisway, contacts and leads can be freely attached to the face of the waferin which the junction areas are formed without danger of creatingmicrowave losses. The high resistivity of the silicon wafer is essentialto avoid microwave losses.

To achieve the requisite high resistivity, one would ordinarily conceiveof using ultra high purity, zone refined silicon. Whereas the use ofthis material would be more than acceptable from a technical standpoint,viewed from economy, its use would be prohibitive. Thus the inventionhas sought and found a way of procuring silicon of necessary resistivitywithout incurring the expense one would normally associate with thisachievement. High resistivity silicon satisfactory for this invention isproduced by gold plating the silicon wafer and thereafter diffusing thegold plating into the wafer at a temperature of about 800 C. for about24 hours. This diffusion of gold increases the resistivity of thesilicon in the order of a few thousand ohm-centimeter or more. It hasbeen found that gold has the property of compensating for any impuritiescontained in the silicon. The gold establishes recombination centers inthe silicon crystal and thus decreases the lifetime of the carriers andwould not normally suggest itself as being a good material to be addedto the silicon. However, in the application of microwave detection, thelifetime of the carriers is not an important consideration. It is notimportant whether the silicon has a high, medium or low resistivityinitially, as the addition of gold will drive the silicon to a very highresistivity. Consequently, a lower purity silicon may be used as a rawmaterial and a high resistivity still be obtained.

Iron or copper could be used instead of gold but these elements do notwork as well. The diffused material should have an energy level thatlies deep in the forbidden band, whereas the normal impurities added toa semiconductor crystal lie very close to either the conduction or thevalence band. Such normal impurities would include B, Al, Ga, In, P, As,Sb, etc. Gold has several levels but all of them are close to the middleof the forbidden band and as a result, gold would have to be heatedconsiderably before it would contribute to the conductivity of theparent material. The amount of gold needed for the diffusion is veryminute as the concentration achieved is about 10* to10- parts to onepart of the semiconductor material.

After the above-described diffusion process, the excess gold is removedand one surface of the wafer is lapped flat. Grooves are then cut intothis surface to a depth of three to five mils to form ridges and valleysof substantially equal width. The cutting of these grooves is carriedout by placing four strips of tape on the lapped surface parallel toeach other and then, using the tape as a mask, forming the grooves bysand blasting. The tapes employed were made of Teflon, although any thintape could be suitably used so long as the proper mechanical maskingwere provided. After sand blasting, the wafer is etched with a fast etchmaterial, such as CF 4, which comprises hydrofluoric acid, nitric acid,acetic acid and a small amount of bromine, to remove the rough surfacescaused by the sand blasting and to remove the surface region exhibitingmechanical strain. This step insures that the diffusing step which takesplace next will not be preferential along strain lines, cracks, or thelike. Instead of being etched, the wafers could be polished with asuitable brass or cast iron material.

Following the etching step, phosphorous from the vapor state is diffusedinto the surface of the solid state wafer in an open tube process. Thisdiffusion is carried out in an oxygen atmosphere at a temperature of1300 C. for a period of 30 minutes. As a result, an air-tight layer ofN-type material is formed in the valleys or grooves and on the ridges orlands of the wafer to a depth of about .0003 inch. The oxygen atmosphereproduces a layer of oxide on the surface of the diffused layer. Thephosphorous doped material is then removed or cut away from the top ofthe ridges or lands by lapping and mechanical polishing leaving anN-type layer covered with oxide in the valleys or grooves. This lappingand polishing operation is carried out by using a fairly coarse grindingcompound to remove a layer of about .001 inch thick and then using avery fine polishing compound such as cerium oxide polish to produce agood optical polished surface. Following the polishing operation, thewafer is washed and then boron is diffused into the wafer. Thi borondiffusion is carried out at a temperature from 1200 to 1250 C. for aperiod of from to 30 minutes in a dry oxygen atmosphere. The borondiffuses into the ridges and forms a layer of P-type material on each ofthe ridges from .0002 to .0004 inch thick. The oxide coating on theN-type material in the valleys provides a partial masking against theboron diffusion. Thus, after this step of boron diffusion, there arealternate strips of P and N-type material corresponding to the ridgesand valleys on the wafer surface. The steps of phosphorous diffusion andboron diffusion are controlled so that the boron concentration in thelayer on the ridges is less than the phosphorous concentration in thelayers in the valleys in order to get good junctions. This difference inthe diffusion steps helps offset the partial diffusion of boron into thephosphorous doped layers in the valleys.

In FIGURES 1 and 2, which illustrate the wafer after the diffusionsteps, the reference numeral 11 designates the wafer. The layers 13 ofN-type material cover the valleys and extend up to the corners of theridges. The layers 12 of P-type material extend over the top of theridges. Diode junctions 14 are formed at the intersection of the layers12 and 13. The exact position and shape of the junctions is not knownbut they occur somewhere near the corners of the ridges.

After the step of diffusing boron, small wires are stretched across thegrooved surface of the wafer 11 in contact with the ridges andperpendicular to the direction of the laterally extending ridges andgrooves. The wires 15 are about .010 inch in diameter. After the wires15 are positioned as shown in FIGURES 1 and 2, the grooved surface isagain sand blasted to cut below the surface layers 12 and 13. The wires15 provide a mechanical mask in the sand blasting and as a result grooveare cut between the wires 15 leaving lands in the shadows of the wires.FIGURE 3 illustrates a cross section of the wafer perpendicular to thecross section shown in FIG- URE 2 after this second sand blastingoperation has taken place. As shown in FIGURE 3, the grooves cut betweenthe wires 15 extend below the strips or layers 13 of N- type material.

The resulting product, shown in FIGURE 4, comprises eight strips ofdoped material on the silicon wafer 11 with each strip comprisingalternate layers 12 and 13 of N and P-type material. There are eightdiodes (four back-to-back diodes) fabricated on each strip so 64 diodesin all are formed. In order for these diodes to be good microwavesdetectors, they must have a low shunt capacitance and a low resistivity.The shunt capacitance is made low by making the area of the diode smallwhich is accomplished by the wire masking and sand blasting techniques.Also the shunt capacitance is decreased by having a high resistivitymaterial on each side of the diode. Ordinarily this desire for highresistivity material on each side of the diode would be in opposition tothe need for low resistivity diodes. However, by using the base materialwith gold diffused therein, the two extremes are obtained. The diffusedgold causes the base material to have a high resistivity and the diodesthemselves to have a low resistivity. The high resistivity base materialused also enables the diodes to operate effectively as if they wereisolated from each other.

The width of the wire used in the sand blasting operation controls thewidth of the strip of diodes and thus control the impedance of thediodes. Thus, the impedance of the diodes may be selected to match theimpedance of the incoming microwaves.

Instead of the sand blasting steps described above, photo-resist maskingand etching could be used to cut the grooves. Photo-resist is aphotographic plastic material that would be applied to the surface. Thenthose parts of the surface which it is desired to mask are exposed toultraviolet light which hardens the material. The hardened material thenserves as a mask in the etching process.

As will be evident from the above, 64 diodes are produced in an area 1inch square or less. The wafers which are produced by this process canthen be mounted to completely cover one hemisphere of a Lunberg lens andthe other hemisphere used as the collecting lens to focus microwaveenergy on the diode array. Approximately a quarter of a million diodeswould be mounted on the one hemisphere of the lens and a satisfactoryresolution would be obtained. By appropriately scanning the diodes suchas by sequentially sampling their outputs, a picture can be built up ona suitable display device such as a cathode ray tube. It will probablybe advantageous for the scanning to be subdivided into sectors and aplurality of independently scanning arrangements to be used each havingits own associated CRT.

Many other modifications may be made to the above described preferredembodiment of the process and product without departing from the spiritand scope of the invention, which is limited only as defined in theappended claims.

What is claimed is:

1. .A method for making semiconductor devices comprising the steps of 2(a) providing a monocrystalline semiconductor body having a plurality ofgrooves at selected first locations of a surface of said body and aplurality of lands of said grooves at selected second locations of saidsurface,

(b) diffusing into said surface from an oxygen atmosphere containingphosphorus to change said surface to N-type conductivity and form adiffusion masking coating of oxide upon said surface,

(c) selectively removing said diffusion masking coating of oxide andsaid changed N-type conductivity surface from the said lands of saidgrooves, thereby to leave a plurality of first diffused regions ofN-type conductivity at said selected first locations of said surface,each of said plurality of first diffused regions extending to saidsurface beneath unremoved oxide,

(a) diffusing boron impurities into said lands to form a plurality ofsecond diffused regions of P-type conductivity adjoining the saidplurality of first diffused regions of N-type conductivity at saidsurface, and

(e) forming another plurality of grooves at said surface perpendicularto the original grooves to form a series of separated surface adjacentjunction devices having their P-type conductivity region injuxtaposition with said N-type conductivity region at said sur face.

2. A method for making semiconductor devices comprising steps of:

(a) forming a plurality of first diffused N-type conductivity regionsbeneath selected first locations of a surface of a monocrystallinesemiconductor body, each of said plurality of first diffused N-typeconductivity regions extending to said surface beneath oxide material,

(b) selectively diffusing P-type conductivity impurities into exposedportions of said surface of said body at selected second locations ofsaid surface outside of and in juxtaposition wtih said selected firstlocations, and

(c) selectively removing portions of said surface to form a series ofseparated surface adjacent junction devices.

3. A method for fabricating a high frequency semiconductor devicecomprising the steps of:

(a) providing a high resistivity monocrystalline semiconductor bodysubstantially free of conductivity determining type impurities therein.

(b) forming a plurality of first diffused regions of one conductivitydetermining type beneath selected first locations of a major face ofsaid body, each of said plurality of first diffused regions extending tosaid major face beneath diffusion masking material upon said major face,and

(c) selectively diffusing impurities of opposite conductivitydetermining type into exposed portions of said high resistivitymonocrystalline semiconductor body at .a plurality of selected secondlocations of said major face outside of and in juxtaposition with saidselected first locations, thereby to provide surface adjacent PNjunction areas at said major face.

4. A method for making a semiconductor device comprising the steps of:

(a) forming at least one region containing one conductivity determiningtype impurities at at least one select first location of a surface of ahigh resistivity semiconductor body substantially free of conductivitydetermining type impurities, and

(b) selectively introducing impurities of opposite conductivitydetermining type into at least one select second location of saidsurface of said body to form a second region, said second region beingoutside of and in juxtaposition to said one region and both of saidregions being oriented on said surface.

5. The method as described in claim 4 wherein said one region and saidsecond region are formed by diflusron.

6. A method for making a semiconductor device comprising the steps of:

(a) forming at least one region containing one conductivity determiningtype impurities at at least one select first location of a major face ofa high resistivity body of semiconductor material, said body beingsubstantially free of conductivity determining type impurities, and

(b) selectively forming at least one region containing oppositeconductivity determining type impurities at at least one select secondloc-ation of said major face, said at least one select second locationbeing outside of and in juxtaposition with said at least one selectfirst location.

7. In a method of making a plurality of surface-oriented semiconductordevices within a single body of high resistivity monocrystallinesemiconductor material substantially free of conductivity determiningtype impurities, said body having a plurality of first diffused regionsof one conductivity type beneath selected first locations of a majorface of said body, each of said plurality of first diffused regionsex-tending to said major face beneath a diffusion m-asking coating, thestep of selectively diffusing impurities of opposite conductivity typesolely into selected second locations outside of and in juxtapositionwith said selected first locations along said major face, thereby toprovide a plurality of surface-oriented semiconductor devices along saidmajor face of said body.

References Cited UNITED STATES PATENTS 3,083,441 4/1963 Little 148-189 X3,160,539 12/1964 Hall .148-1.5 X 3,183,128 5/1965 Leistiko 148-1872,860,218 1/1958 Dunlap 148-177 X 2,981,877 4/1961 Noyce 148-187 X3,005,937 10/1961 Wallmark 148-33.2 X 3,020,412 2/1962 Byczkowski317-234- X 3,022,568 2/1962 Nelson 148-1.5 X 3,122,817 3/1964 Andrus148-187 3,144,366 8/1964 Rideout 148-187 X 3,183,129 5/1965 Tripp148-189 X 3,151,007 9/1964 Dahlberg 148-187 HYLAND BIZOT, PrimaryExaminer.

1. A METHOD FOR MAKING SEMICONDUCTOR DEVICES COMPRISING THE STEPS OF:(A) PROVIDING A MONOCRYSTALLINE SEMICONDUCTOR BODY HAVING A PLURALITY OFGROOVES AT SELECTED FIRST LOCATIONS OF A SURFACE OF SAID BODY AND APLURALITY OF LANDS OF SAID GROOVES AT SELECTED SECOND LOCATIONS OF SAIDSURFACE, (B) DIFFUSING INTO SAID SURFACE FROM AN OXYGEN ATMOSPHERECONTAINING PHOSPHORUS TO CHANGE SAID SURFACE TO N-TYPE CONDUCTIVITY ANDFORM A DIFFUSION MASKING COATING OF OXIDE UPON SAID SURFACE, (C)SELECTIVELY REMOVING SAID DIFFUSION MASKING COATING OF OXIDE AND SAIDCHANGED N-TYPE CONDUCTIVITY SURFACE FROM THE SAID LANDS OF SAID GROOVES,THEREBY TO LEAVE A PLURALITY OF FIRST DIFFUSED REGIONS OF N-TYPECONDUCTIVITY AT SAID SELECTED FIRST LOCATIONS OF SAID SURFACE, EACH OFSAID PLURALITY OF FIRST DIFFUSED REGIONS EXTENDING TO SAID SURFACEBENEATH UNREMOVED OXIDE, (A) DIFFUSING BORON IMPURITIES INTO SAID LANDSTO FORM A PLURALITY OF SECOND DIFFUSED REGIONS OF P-TYPE CONDUCTIVITYADJOINING THE SAID PLURALITY OF FIRST DIFFUSED REGIONS OF N-TYPECONDUCTIVITY AT SAID SURFACE, AND (E) FORMING ANOTHER PLURALITY OFGROOVES AT SAID SURFACE PERPENDICULAR TO THE ORIGINAL GROOVES TO FORM ASERIES OF SEPARATED SURFACES ADJACENT JUNCTION DEVICES HAVING THEIRP-TYPE CONDUCTIVITY REGION IN JUXTAPOSITION WITH SAID N-TYPECONDUCTIVITY REGION AT SAID SURFACE.